Dynamic random access memories (DRAMs) contain many millions of memory cells on a single integrated circuit (IC) chip and are capable of operating at very high clock rates. It is customary to provide on a separate integrated circuit an array of input receivers and output drivers to provide input binary signals to be stored in the memory and subsequently to output these binary signals to other circuitry as desired. In order to take full advantage of the high switching speed capability of a DRAM, the drivers, which are denoted as off chip drivers (OCDs), need to be capable of operating at very high clock rates, for example, at hundreds of megahertz.
Each of the off chip drivers on an IC chip, which itself is connected via pins and bond wires to other circuitry, is connected between at least two voltage supply buses on the chip which power the drivers. But because of physical constraints and space considerations in the layout of the drivers on the chip, some of the drivers are connected closer to the input ends of the voltage supply buses and other are connected much further away. Even though distances can be very short (e.g., a few millimeters or less), the inherent electrical inductances of the chip pins and bond wires and the electrical resistances of the buses become significant as clock rates are pushed higher and higher. Resistive voltage drops along a power supply bus from one driver to the next, and cumulatively along the length of a bus can become large enough to cause undesirable noise effects and troublesome differences in speeds or times of operation of the respective drivers on a circuit chip. These differences in speed are particularly marked when almost all of the off chip drivers are outputting binary "1's", for example, and only one or a few are outputting binary "0's" (or vice versa). As clock rates are pushed higher and higher in order to realize the full benefits of high speed DRAMs, the respective times of switching amongst previously known off chip drivers on a chip differ more and more and this results in greater and greater "TSSO" errors. Such a situation can seriously limit proper operation of a computer, for example. It is important therefore to eliminate, or at least significantly reduce such noise effects and timing errors.
It is thus desirable to reduce the above described problems of integrated circuit off chip drivers and thus to facilitate high speed operation.